Ivan Kokshaysky wrote:
>
> Hmm, what happens if you boot the kernel configured for 80386
> on P4 and enable MWI?
Which answer is better?
- It works safely: pci cache line size not less than the real one.
- There's I/O-pattern dependant breakage caused by that config goof.
I think the first answer is better, but it looks like 2.5.59 will
set the pci cache line size to 16 bytes not 128 bytes in that case.
The generic pci code to set cacheline size uses SMP_CACHE_BYTES,
which is usually L1_CACHE_BYTES ... and looks incorrect at least on
non-SMP ia64. Only sparc64 seems to have non-generic code to set
the line size but it's done for all devices, as they're probed.
Maybe i386 should HAVE_ARCH_PCI_MWI, smart enough to use the actual
CPU's cache line size (boot code saves that, yes?) and maybe even
check for that particular class of breakage Anton mentioned.
Another option would be to do like SPARC64 and set the cacheline
sizes as part of DMA enable (which is what I'd first thought of).
And have the breakage test in the ARCH_PCI_MWI code -- something
that sparc64 doesn't do, fwiw.
- Dave
-
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This archive was generated by hypermail 2b29 : Fri Jan 31 2003 - 22:00:24 EST