On Thu, Jan 30, 2003 at 08:25:07AM -0800, David Brownell wrote:
> At least on 2.5.59, the pci_generic_prep_mwi() code doesn't check
> for that type of error: it just writes the cacheline size, and
> doesn't verify that setting it worked as expected. Checking for
> that kind of problem would make it safer to call pci_set_mwi() in
> such cases ... e.g. using it on a P4 with 128 byte L1 cachelines
> would fail cleanly, while on an Athlon (64 byte L1) it might work
> (depending in which top bits are unusable).
Hmm, what happens if you boot the kernel configured for 80386
on P4 and enable MWI?
Ivan.
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