On Mon, 22 May 2000, Dragan Stancevic wrote:
> On Mon, May 22, 2000, Donald Becker <becker@scyld.com> wrote:
> ; > changes so you might not satisfy the minimal clock frequency
> ; > specification.
> ;
> ; The very old code used eeprom_delay(100), which mean 100ns, *not* 100usec.
>
> If I greep the driver that was in 2.2.6 kernel I get
>
> #define eeprom_delay(nanosec) udelay(1);
> eprom_delay(100);
> eprom_delay(150);
>
> So the "nanosec" parameter gets trashed and you delay
> for 1 us in all of the cases.
Well, there isn't a nanodelay(nsec) function.
And, as you know, udelay() isn't reliable on some kernel versions.
The usual maximum clock rate is 2.5Mhz or 4Mhz.
That's 250 or 400ns per cycle, or 125/200ns per half cycle.
A 33Mhz PCI bus transaction will take a minimum of 120ns, likely more.
Donald Becker becker@scyld.com
Scyld Computing Corporation
410 Severn Ave. Suite 210
Annapolis MD 21403
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