> > We have recent technology DEC laptops that require timing delays on the
> > keyboard controllers are honoured for that matter
>
> This is not the keyboard controller.
Odd but the DEC engineer I talked to says it is.
> > You might suggest using udelay() here but unfortunately we cannot calibrate
> > udelay until the TSC is programmed so that is out too.
>
> This is not necessary. Although "xor cx,cx ; loop $" will satisfy
> pedantics during the one-time setup of the chip.
256 clocks. Assuming parallel execution of both instructions 128 clocks. 128
clocks at 1GHz, is 8uS. So for likely future cpus we can assume it gets you
2uS - ok. Providing of course transmeta doesnt code morph it out !
> The IRQ, if it happens, will break everything anyway. You can't do
>
> out 0x20, 0x11 ; Start setup sequence
> ... get interrupted
> out 0x20, 0x20 ; ISR sends EOI to controller.
>
> ... so this is not relavant. The mask registers, 0x21, and 0xA1 have
> been masked off in setup.S anyway.
Good point.
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