Are you kidding? Do you really want to use that on device's registers ?
>
> Bret> Modern processors are in excess of 200 MHz. That would come out
> Bret> to about 5 ns/cycle. The processor can execute 12 instructions
> Bret> in the time it takes to do the minimum PCI cycle. That should be
> Bret> more than enough time to do a minimal subroutine call. The
> Bret> faster your processor, the worse it gets.
>
> Faster your processor, the deeper your pipeline, branch == pipeline
> flush. next?
Ok, branch has a penalty but it's certainly != pipeline flush.
Note that this is unconditional branch, and if the branch target address
is computed sufficiently ahead of the branch instruction there will be
no penalty.
> And here you might want to look at some of the released
> documentation on the IA64 to see what we might expect from the future,
> branches are expensive.
Have Intel released docs about some implementation of the architecture ?
OTOH, judging from past experience, I wan't be surprised
if Intel ain't got it Right *again*. (OK, OK, just kidding,
people (and companies) sometimes grow up and learn things :-)
Regards,
-velco
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