Re: PCI cache incoherency and DMA
Philip Blundell (Philip.Blundell@pobox.com)
Sat, 21 Aug 1999 22:49:16 +0100
>Also, in io.h, there are some macros defining (or not defining depending
>on the architecture) the flush and invalidate routines for DMA. That's
>great, but there are at least 2 important informations missing from this
>header file in order to write safe drivers:
>
> - The cache line size (I beleive it may be defined elsewhere, is there a
>standard #define for it ?)
>
> - and wether we are coherent or not. For the coherency, this is more
>complicated since it depends on the bus we are on.
Why do you need these pieces of information? All this stuff should be taken
care of by the macros. Just call dma_cache_inv() or whatever and pass it the
true size of the region you are interested in; it will calculate how many
cache lines are affected and deal with them appropriately. For buses where
coherency is guaranteed this is a no-op.
p.
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