They aren't PCI compliant if they don't decode all 32 bits. Extract from
PCI v2.1 spec:
"The I/O Read command is used to read data from an agent mapped in I/O
Address Space. AD[31::00] provide a byte address. All 32 bits must be
decoded."
Ditto for I/O write. The area where PCI devices are likely to cheat on
address decoding is in the IO/mem base address regs, where some bits may
be hardwired to zeros.
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