> On Thu, 10 Jun 1999, B. James Phillippe wrote:
>
> > Greetings,
> >
> > With regard to hardware interrupt servicing on 2.2, how are nested
> > interrupts handled on UP? From reading the code, it appears that they are
>
> In UP in ix86, the two cascaded interrupt controllers are used. When an
> interrupt occurs, before the driver ISR is called, that one particular
> interrupt level is masked off. Therefore, the ISR will not be reentered.
Sorry, this is the right answer to the wrong question; I'm aware of how the
situation works for that same IRQ, but that's not what I'm asking about.
I'm asking about nested dissimilar interrupts, not re-entered interrupts.
Like this:
Slow Interrupt A ISR entered (ie. no SA_INTERRUPT)
Interrupt A already disabled in interrupt controller
Other interrupts still enabled in controller and microprocessor
----Interrupt B for unrelated device is asserted, ISR B entered
Interrupt B disabled in interrupt controller
Other interrupts still enabled in IC and CPU
----Interrupt B finishes
Stack unwound, interrupt A ISR resumes
Interrupt A ISR finishes
Is this possible? It appears to be possible on x86, but not on Alpha (ie.
on Alpha in arch/alpha/kernel/irq.c, interrupt reporting is disabled in the
microprocessor prior to ISR execution). In the x86 case, if it is
supported (as it appears to be), how deep can this happen? Is it only
limited by available number of interrupts that can possibly fire before
they are all masked off?
-bp
-- # bryan at terran dot org # http://www.terran.org/~bryan
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