There are quite a few of these about. the MP specs have a whole section
devoted to the seven MPC default types (2 CPU SMP machines with no BIOS
interrupt information). I have one under my desk at the moment (a type 2).
Of all these types, 5 (ISA+PCI) is given the least attention in the spec,
presumably because Intel didn't really expect anyone building something as
expensive as an SMP board would use such a cheap and cruddy bus as ISA.
MPC default boards are usually in older machines, but still must be supported.
hubert.tonneau@easynet.fr said:
> The obvious way to do the patch properly is to modify the function
> that generates the IRQ table when it's empty at Bios level, and use
> ELCR register there, and only there, if it's value is not the one of
> an unused IO port. This has never been tryed and must be.
The problem is that a non-existent I/O port doesn't produce a defined value on
a read. The value will usually float to the pull resistors, but may give
random bits on iffy boards. There is too little sanity information in the
ELCR to make a reliable determination of whether you have a bogus value or not.
However, this is open source; code this solution and see how it behaves on
other MPC type 5 boards. I'd suggest using the clock IRQ trigger bit as sanity
(it must be edge in all configurations).
James
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