Finally I'm able to come back to the discussion of this problem. Now it's
showing up on a Dell PowerEdge 1300 (a pretty new system, I must say ...),
and the information for the "failing" system comes from this PowerEdge.
Just to refresh your minds, the problem is that a PLX9080-based PCI board
has an I/O address assigned to it when it actually requested a 32-bit
memory address (more specifically, the PCI Base Address 2).
As of the last status of this thread, I was supposed to try the following
steps:
On Mon, 19 Apr 1999, Linux Lists wrote:
>
> - 'lspci -H1 -vvx' with the latest pciutils (Martin Mares);
Ok, let's compare the outputs (both systems running kernel 2.0.36):
1. Output from a working system (i.e., my development system):
----------------------------------------------------------
00:12.0 Communication controller: Cyclades Corporation Cyclom_Z above
first megabyte (rev 01)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32 set
Interrupt: pin ? routed to IRQ 255
Region 0: Memory at e0310000 (32-bit, non-prefetchable)
Region 1: I/O ports at 6200
Region 2: Memory at e0200000 (32-bit, non-prefetchable)
00: 0e 12 01 02 07 00 80 02 01 00 80 07 00 20 00 00
10: 00 00 31 e0 01 62 00 00 00 00 20 e0 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00
2. Output from the failing system (i.e., the PowerEdge):
----------------------------------------------------
02:09.0 Communication controller: Cyclades Corporation Cyclom_Z above
first megabyte (rev 01)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 32 set
Region 0: Memory at f9fffc00 (32-bit, non-prefetchable)
Region 1: I/O ports at dc80
Region 2: I/O ports at f9e00000
00: 0e 12 01 02 07 01 80 02 01 00 80 07 00 20 00 00
10: 00 fc ff f9 81 dc 00 00 01 00 e0 f9 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00
Differences:
-----------
- SERR disabled on working system, enabled on failing system (I don't
know what that means);
- Base Address 2 allocates 32-bit memory on working system, I/O on failing
system;
> - apply provided patch and check whether it makes a difference (Gerard
> Roudier);
It didn't make any difference.
Please comment on these results.
TIA and Regards,
Ivan
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