>Intel (and possibly other) motherboard chipsets allow changing the area
>between 0xc0000 and 0x100000 to cacheable ram. Look at their web site for
>docs.
I didn't known that the i386 architecture was mapping such ram for other
purposes (I thought that leaving the 8086 mode would have killed also all
obsolete annoying features). But reading your email looks like that the
ISA I/O space is memory mapped in such space (but the old 8086 was the
opposite of a memory mapped CPU and every I/O was done with outb/inb, so
why the need of a memory mapped area in the middle of the RAM (... really
at that time it was at the end of the RAM ;).
>int init_module(void)
>{
> unsigned long i;
> for (i=0x9f000+PAGE_OFFSET; i < 0xa0000+PAGE_OFFSET; i+=PAGE_SIZE) {
> clear_bit(PG_reserved, &mem_map[MAP_NR(i)].flags);
> }
> for (i=0xc0000+PAGE_OFFSET; i < 0x100000+PAGE_OFFSET; i+=PAGE_SIZE) {
> clear_bit(PG_reserved, &mem_map[MAP_NR(i)].flags);
> }
You forgot:
atomic_set(&mem_map[MAP_NR(i)].count, 1);
free_page(i);
Otherwise the memory won't be used by the kernel.
I am not checking if it works here because 300k are not an issue but I am
not very happy to know that I am losing 300k of RAM by default anyway...
Andrea Arcangeli
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