Re: SMP vs. Specialized chipsets WAS: Re: I have information/driver ...

Kurt Garloff (K.Garloff@ping.de)
Thu, 15 Apr 1999 23:39:50 +0200


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On Thu, Apr 15, 1999 at 02:04:11PM -0700, bwoodard@cisco.com wrote:
> > The ix86 insn set is hard to support with a simple design. Actually, wh=
at
> > K6, PII and PIII do is to translate those insns in internal RISC like i=
nsns
> > which can be nicely handled by the execution units.
> >=20
> > If you want to get rid of that much silicone, you have to dwitch
> > architecture and use PPC, ARM, Alpha or whatever ...
> >=20
> > On the other hand, the x86 code is very dense, resulting in relatively =
short
> > executables.
> >=20
>=20
> One more question then. Since ix86 instruction set is so easy to
> support what takes up all the die space?

Sorry? Did you read what I wrote?
I said: The ix86 insns set is hard to support.
You got a lot of instructions with a lot of modes and different lengths with
few registers. That's an old CISC design.

> Also I still don't understand why chip designers don't design simpler
> chips that behave like multiple processors rather than going to all
> the work of having deep pipelines and all the complexity associated
> with that e.g. speculative execution, out of order execution...=20
> i.e. Is there some reason they don't make a chip which is essentially
> four 486's, cache and all the glue circuitry needed to make them
> capable of running SMP.

Well. Most OSes out there don't support SMP. Also, there are apps, which
don't profit much from multiple processors. Also note, that if 10% of your
app is not parallelizable, you will at most get 10 times the performance of
a single CPU by using multiple. Not counted communication overhead.

Maybe processor designers find it
more exciting to have those nighty features like specul. execution etc.=20
One goal is to build a single very performing CPU. Consider the AXP-21264,
which I consider the most performant affordable chip out there. The AXp is a
RISC design, no question. But with the 21264, a lot of extra logic, such as
spec. execution, more than one insns per cycle, etc. was added. So, the
21264-500 outperforms the 21164-633 by a factor of 1.5 to 2.0 (!)

If you need plenty of performance, you will get several of those.

Regards,

--=20
Dipl.Phys. Kurt Garloff <kurt@garloff.de> [Wuppertal, FRG]
Plasma physics, high perf. computing [Linux-ix86,-axp, DUX]
PGP key: see mailheader / key servers [Linux SCSI driver: DC390]

--y0ulUmNC+osPPQO6
Content-Type: application/pgp-signature

-----BEGIN PGP SIGNATURE-----
Version: 2.6.3in

iQCVAwUBNxZcphaQN/7O/JIVAQHkZgP+OUYSxyXrzCCCLucuZJuvx2YxNeO+d2UF
bsX55w9YONVUSA2n9oGLXfcl/h8uE48W1hcGUjmL/HD8U4VkUWpOPe1AkbvKrRdq
ACiIc6s7z+R9vLz4UIhAyg1dbtXpk1wYMgNvS1AnoOaMLTCnGDCg2+7jnF3Zim8t
WoxGkmt4ELA=
=83q3
-----END PGP SIGNATURE-----

--y0ulUmNC+osPPQO6--

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