> On Tue, 30 Mar 1999, Ingo Molnar wrote:
>
> >why do you worry about instruction prefetch? cache misses and busmaster
>
> Ask to Tigran ;).
I do not worry about instruction prefetch, it is the instruction retire
that I worry. I don't care what is prefetched but if %edx:%eax contains
the value as if the second rdtsc was retired, whilst the stuff in between
the two rdtsc has not been retired - that is bad.
> >DMA makes timings quite random anyway. The only thing we really want is
> >that rdtsc should not be reordered by the compiler (ie. delta time should
> >not be negative), which is already fixed in 2.2.5.
>
> Well I have to admit that playing with MikeG's code today I am been
> convinced that __volatile__ is sure better even it wasn't a bug in the
> current kernel ;).
OK. :)
> · Reads may not pass locked instructions like XCHG
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> While instead:
> · Instruction fetch may pass locked operations like XCHG
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> · Instruction fetch may not pass serializing instructions
Well, here is even clearer one from page 7-12 (volume 3):
Nothing can pass a serializing instruction, and serializing instruction
cannot pass any other instruction (read, write, instruction fetch, or
I/O).
I think cpuid is usually quoted as a "good" serializing instruction
because it can be used in ring3 (and thus tried out by userspace readers
of Intel manuals), whilst others (mov to cr, mov to dr,
wrmsr, invd, invlpg, wbinvd, lgdt, lldt, lidt, ltr) are only suitable in
ring0. But we _are_ in ring0, so we _can_ choose what we like over cpuid.
Regards,
Tigran.
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/