>why do you worry about instruction prefetch? cache misses and busmaster
Ask to Tigran ;).
>DMA makes timings quite random anyway. The only thing we really want is
>that rdtsc should not be reordered by the compiler (ie. delta time should
>not be negative), which is already fixed in 2.2.5.
Well I have to admit that playing with MikeG's code today I am been
convinced that __volatile__ is sure better even it wasn't a bug in the
current kernel ;).
>locked memory operations _are_ serializing instructions (spinlocks would
No. They are serializing only _reads_ in memory (writes are ordered by
default).
Here a cut-and-paste of an Intel spec:
· Reads may not pass serializing instructions like CPUID
· Reads may not pass I/O instructions
· Reads may not pass locked instructions like XCHG
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
While instead:
· Instruction fetch may pass reads
· Reads may not pass instruction fetch
· Instruction fetch may pass I/O
· Instruction fetch may pass locked operations like XCHG
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
· Instruction fetch may not pass serializing instructions
^^^ ^^^^^^^^^^^^^^^^^^^^^^^^
Andrea Arcangeli
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