Re: UDMA not supported on my board

CaT (cat@zip.com.au)
Sat, 13 Mar 1999 20:54:59 +1100 (EST)

Andre M. Hedrick wrote the following:
>
> cat /proc/ide/ali

Still dunno what this is...

> Second :: lspci -bvvxxd 10b9:1533 and lspci -bvvxxd 10b9:5229
> contents would tell me a lot also.

1047.root@kinder:/usr/local/src/pciutils-1.10>> lspci -bvvxxd 10b9:1533
1048.root@kinder:/usr/local/src/pciutils-1.10>> lspci -bvvxxd 10b9:5229

Ummmm.... that's all I got. Erk? I removed the -d option and got the
following though. hope it's more then jsut spam. :)

1046.root@kinder:/usr/local/src/pciutils-1.10>> lspci -vvxxb | more
00:00.0 Class 0600: 8086:7190 (rev 02)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 64 set
Region 0: Memory at e0000000 (32-bit, prefetchable)
Region 1: Memory at <unassigned> (32-bit, non-prefetchable)
Region 2: Memory at <unassigned> (32-bit, non-prefetchable)
Region 3: Memory at <unassigned> (32-bit, non-prefetchable)
Region 4: Memory at <unassigned> (32-bit, non-prefetchable)
Region 5: Memory at <unassigned> (32-bit, non-prefetchable)
00: 86 80 90 71 06 00 10 22 02 00 00 06 00 40 00 00
10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00

00:01.0 Class 0604: 8086:7191 (rev 02)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
Status: 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 64 set
Region 0: Memory at <unassigned> (32-bit, non-prefetchable)
Region 1: Memory at <unassigned> (32-bit, non-prefetchable)
Bus: primary=00, secondary=01, subordinate=01, sec-latency=64
I/O behind bridge: 0000e000-0000efff
Memory behind bridge: e4000000-e7ffffff
Prefetchable memory behind bridge: e8000000-e8ffffff
BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B+
00: 86 80 91 71 07 01 20 02 02 00 04 06 00 40 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 40 e0 e0 a0 22
20: 00 e4 f0 e7 00 e8 f0 e8 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88 00

00:07.0 Class 0601: 8086:7110 (rev 02)
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 0 set
Region 0: Memory at <unassigned> (32-bit, non-prefetchable)
Region 1: Memory at <unassigned> (32-bit, non-prefetchable)
Region 2: Memory at <unassigned> (32-bit, non-prefetchable)
Region 3: Memory at <unassigned> (32-bit, non-prefetchable)
Region 4: Memory at <unassigned> (32-bit, non-prefetchable)
Region 5: Memory at <unassigned> (32-bit, non-prefetchable)
00: 86 80 10 71 0f 00 80 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:07.1 Class 0101: 8086:7111 (rev 01) (prog-if 80)
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 64 set
Region 0: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
Region 1: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
Region 2: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
Region 3: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
Region 4: I/O ports at f000
Region 5: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
00: 86 80 11 71 05 00 80 02 01 80 01 01 00 40 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:07.2 Class 0c03: 8086:7112 (rev 01)
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 64 set
Interrupt: pin D routed to IRQ 255
Region 0: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
Region 1: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
Region 2: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
Region 3: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
Region 4: I/O ports at 6400
Region 5: Memory at <unassigned> (32-bit, non-prefetchable) [disabled]
00: 86 80 12 71 05 00 80 02 01 00 03 0c 00 40 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 64 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 04 00 00

00:07.3 Class 0680: 8086:7113 (rev 02)
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Region 0: Memory at <unassigned> (32-bit, non-prefetchable)
Region 1: Memory at <unassigned> (32-bit, non-prefetchable)
Region 2: Memory at <unassigned> (32-bit, non-prefetchable)
Region 3: Memory at <unassigned> (32-bit, non-prefetchable)
Region 4: Memory at <unassigned> (32-bit, non-prefetchable)
Region 5: Memory at <unassigned> (32-bit, non-prefetchable)
00: 86 80 13 71 03 00 80 02 02 00 80 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:0c.0 Class 0400: 11d1:01f7
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 64 set
Interrupt: pin A routed to IRQ 11
Region 0: Memory at e9000000 (32-bit, non-prefetchable)
Region 1: Memory at <unassigned> (32-bit, non-prefetchable)
Region 2: Memory at <unassigned> (32-bit, non-prefetchable)
Region 3: Memory at <unassigned> (32-bit, non-prefetchable)
Region 4: Memory at <unassigned> (32-bit, non-prefetchable)
Region 5: Memory at <unassigned> (32-bit, non-prefetchable)
00: d1 11 f7 01 07 00 80 02 00 00 00 04 00 40 00 00
10: 00 00 00 e9 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00

01:00.0 Class 0300: 102b:0521 (rev 01)
Subsystem: 102b:ff03
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16 min, 32 max, 64 set, cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: Memory at e8000000 (32-bit, prefetchable)
Region 1: Memory at e4000000 (32-bit, non-prefetchable)
Region 2: Memory at e5000000 (32-bit, non-prefetchable)
Region 3: Memory at <unassigned> (32-bit, non-prefetchable)
Region 4: Memory at <unassigned> (32-bit, non-prefetchable)
Region 5: Memory at <unassigned> (32-bit, non-prefetchable)
00: 2b 10 21 05 07 00 90 02 01 00 00 03 08 40 00 00
10: 08 00 00 e8 00 00 00 e4 00 00 00 e5 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 03 ff
30: 00 00 00 00 dc 00 00 00 00 00 00 00 0b 01 10 20

-- 
CaT (cat@zip.net.au)                       URL: http://www.zip.com.au/dev/null


   An electricity provider of New Hampshire, US has advised it's customers
   that in the event of a power failure they can log on to its website for
   more information...   - Paraphrased from the New Scientist, Feb 6, 1999




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