So I'm purusing the specs on the 21172 chip (the LX/UX/SX memory and PCI
controller chip, aka Pyxis), and I see the following statement:
"This scheme allows a NATURALLY ALIGNED 1MB to 4GB PCI window to be placed
anywhere in the first 1TB of the 64-bit address space." [21172 Technical
Reference Manual, page 6-34]
The modification that needs to be made is in making PCI memory "windows" and
in the functions virt_to_bus and bus_to_virt (which map physical addresses
to bus addresses and vice versa -- defined in
include/asm-alpha/core_pyxis.h). From the file
arch/alpha/kernel/core_pyxis.c:
* Window 0 goes at 1 GB and is 1 GB large.
The other "windows" are not used.
It seems simple to me to modify these two files to support up to 1TB memory
on the alpha, as opposed to the hard-coded limit of 1GB now. It appears the
21172 will only decode 40 bits of address, not 64, but that's 1TB...
Documentation on this can be found at:
http://ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
I cannot fix this myself (I have only a mere 256 MB of RAM), but send this
in the hopes that someone with enough RAM to test it is willing to fix it.
That is, unless some kind soul wants to donate a few gig to me. ;)
-- Bob
Bob McElrath (rsmcelrath@students.wisc.edu) Univ. of Wisconsin at Madison
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