Ok, I had hoped that because of your email address that you
could answer my question about enabling/disabling the paging
bit on an IA32 chip. I've got several Intel books but nowhere
does it specify exactly what happens when the PG bit is
set/cleared. When the PG bit is set after being cleared does
the processor assume that the TLB is still valid?
The best I've seen is an admonition to put a 'jmp' immediately
after enabling paging for the purpose of flushing the instruction
pipeline; does this work on a Pentium II? I wonder if a 'ret' will
do the same thing.
The multi-segment architecture I described is just an idea of
mine which AFAIK does not correspond to the way Linux or
FreeBSD is organized. In my architecture a portion of the
kernel (low 128K) is mapped with each task and the larger
portion of the kernel runs in an unpaged sparsely populated
physical segment.
Regards,
Norman Culver
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