Re: MSR/performance monitoring for PPro
David Wragg (dpw@doc.ic.ac.uk)
17 Jan 1999 23:28:04 +0000
Richard Gooch <rgooch@atnf.csiro.au> writes:
> Since I have your attention, I'd like to ask another question. Looking
> at table A1 I see event# 0x85 (ITLB_MISS), which appears to be
> instruction TLB misses. There doesn't seem to be a data TLB miss
> event. Am I misinterpreting the 'I' in "ITLB", or does the event I
> want not exist?
I think you're right, because it comes in the "Instruction Fetch Unit"
section.
No, I can't find a corresponding DTLB miss event either, which is
especially odd because the Pentium does have one.
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