MSR/performance monitoring for PPro

Richard Gooch (rgooch@atnf.csiro.au)
Sun, 17 Jan 1999 16:59:00 +1100

Hi, all. While trying to track down the source of variability in a
memory-intensive task (running on a PPro), I've been trying to gain
access to the CPU performance monitoring facilities. I've trawled the
Intel developer's WWW site and all I can come up with is a document
for the Pentium and Pentium/MMX which discusses this. There I see that
MSR# 0x11 is the "Control and Event Select Register". However, any
attempts to read or write this register result in a general protection
fault. I don't have the same problem when reading MSR# 0x10 (the Time
Stamp Counter). Below are some code snippets to show what I'm doing:

#define rdmsr(msr,val1,val2) \
__asm__ __volatile__("rdmsr" \
: "=a" (val1), "=d" (val2) \
: "c" (msr))
unsigned long val1, val2;

rdmsr (0x11, val1, val2);
printk ("vals: %lx %lx\n", val1, val2);

Running the same code on a Pentium seems to work fine. Since the
manual does say that the MSRs can change from model to model, I guess
I shouldn't be too surprised.

So it looks like I need a list of MSRs specifically for the Pentium
Pro. Does anybody have such a list, or a URL I can use?

Aside: reading the Pentium event counters for data TLB miss and data
read miss give odd-looking numbers. The counters seem to switch
between pairs of slowly increasing numbers.

Regards,

Richard....

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