Yes. (My -=*guess*=- is that the CPU can overwhelm the memory
interface. So the CPU gets "stopped", and the PCI master gets a
chance. First thing it does, is write to the memory again. So the
burst transfer gets aborted, and the CPU gets a chance again. Lo and
behold: more memory writes. This way the PCI master would only get to
write a single word at a time, which is very inefficient.)
But, in a later message, you say you don't use the VIDEO pipeline for
this datastream, but the Codec pipline.
The Video pipeline is designed for 0 to 20Mb (Warning: wild guess!)
per second datastreams. The codec pipeline is designed for much slower
datastreams. So it has less "high performance" features. That's from
the point-of-view of the PCI interface chip.
You suggested to wire the "dataerr" line to a general IRQ line on the
'67. That's not neccesary, provided you've wired the '60 JIRQ line to
somwhere where you can catch it. (Section 6.11.1 of the '60 datasheet).
You said that there was a significant buffer. In the '60 I see a 512
byte buffer. That's quite large. The question is, is the '67 capable
of stopping the data-transfer there, if its FIFO is full?
Regards,
Roger.
-- | Most people would die sooner than think.... | R.E.Wolff@BitWizard.nl | in fact, most do. -- Bertrand Russsell | phone: +31-15-2137555 We write Linux device drivers for any device you may have! fax: ..-2138217- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/