> Hello,
>
> I was doing some test on interrupt latency (time from raising an
> interrupt to reading timestamp
> in a handler). I created my own fast handler registered at IRQ32 (
> interrupt is generated by
> the APIC timer on a Ppro 200) that gives me a latency of approx 2300
> nanoseconds
the APIC timer interrupt is a CPU-internal IRQ, and thus has lower
latencies. It should have identical latencies to a software interrupt.
(like your numbers show). I measured 500 cycles _total_ profiling
interrupt cost. This makes it possible to run 100 thousand IRQs a second
profiling on a 100MHz P5. (i've tried it. It's noticeable but it works)
_external_ interrupts have much higher latencies. (especially as old
XT-PIC interrupts halt the CPU for a considerable amount of time ... this
is not the case with IO-APIC and inter-CPU interrupts.)
-- mingo
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