> OK, so here's a question: part of interrupt latency should include
> at least a couple of register reads across the PCI bus.
Won't these speeds vary considerable depending upon whether or not
the device is marked non-prefetchable and the latency of the device?
I've been playing with timing of r/w on PCI video cards in the last
couple of days, and they seem to vary considerable - so, what would
be a good peice of hardware to probe, something thats fairly common
and isn't going to vary greatly from machine to machine?
> Anyway, the deal is that reading/writing state across the bus is
> like an uncached memory access and used to take around a usec or
> so. If, and this shows how little I know, the read/write is 10% or
> so of a null interrupt, then I'd like to include that cost. Any
> ideas?
As several people have suggested, since this pretty much needs to be
arch. specific and done in kernel land, and there are various factors
influencing stuff something like:
isr(){
time.intstart <= rdtsc
do_pci_access()
time.intend <= rdtsc
}
do (many times){
time.preint <= rdtsc
generate_inrerrupt
time.postinnt <= rdtsc
store_values();
}
On the intel, this would give you:
- the time taken for the isr to be invoked (preint - intstart)
- the time taken for dummy pci access (intend - intstart)
- the time taken for the isr to finish (postinnt - intend)
Sound reasonable?
Actually... might just go and code something like that now. If
anybody knows the equivalent of `rdtsc' for the Alpha and Sparc I'd
really like to know that.
-cw
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