On Mon, 3 Aug 1998, Andrew Derrick Balsa wrote:
> Hi Peter,
>
> On Mon, 03 Aug 1998, Peter T. Breuer wrote:
> ....
> >
> >Kernel compilation seems cpu and/or memory bound, and the measurements
> >seem to indicate that the measurements that I make don't distinguish the
> >two.
>
> It's hard to tell unless you keep the other parameter constant, and in the case
> of the Celeron oc.@412MHz vs. PPro200, this is impossible. The Celeron has a
> small 32KB L1 cache and that's it. The PPro has both an L1 cache and an L2
> cache (you didn't say but I assume it is the more common 256KB model).
Not having a L2 cache is a killer to performance. The Celeron is memory
bound in this particular case. GCC uses a lot of memory which, of course,
doesn't fit on the Celeron L1 cache. What we are probably seeing here are
pipeline stalls due to cache misses. These bring a 412Mhz CPU down to a
PPro 200 level. Assuming very similar arch, the Celeron is internaly idle
50% of the time (probably more, since PPro isn't 100% busy). Of course,
rating CPU performace based on Mhz is a well known fallacy.
Cheers,
Rafael
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