I don't understand the problem with partial page pgd/pmd. The page table
cache that i have implemented for m68k works ok.
Yes, it's trivial to make it work fine on machines with only single
processor implementations. Would your version work ok on an SMP
machine and preserve the lockless semantics of the pgt cache?
Actually, you can look at the older UltraSparc code and the Sparc32
port code to see where the hair is, since Jakub's description hasn't
shown the light enough. The code is your teacher :-)
Later,
David S. Miller
davem@dm.cobaltmicro.com
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