Re: 2.1.110 PCI patch for booting an NCR S40

Eric Paire (e.paire@opengroup.org)
Thu, 23 Jul 1998 09:45:19 +0200


I finally found the lspci command:

* Before the patch:
Nothing since I can't boot, the SCSI devices are on the PCI bus #1
which is not recognized by the standard Linux-2.1.110 (there is
no root FS).

* After the patch (lspci -vvx):

00:00.0 Class 0600: 8086:1225 (rev 02)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
Status: 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 2 min, 6 set
00: 86 80 25 12 47 01 00 22 02 00 00 06 00 06 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00

00:0e.0 Class 0000: 8086:0482 (rev 05)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 248 set
00: 86 80 82 04 47 00 00 02 05 00 00 00 00 f8 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:0f.0 Class ff00: 8086:0008
Subsystem ID: fc08:ffe7
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
Status: 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Region 0: Memory at ffe7fc00 (32-bit, prefetchable)
Region 1: Memory at ffe7fc00 (32-bit, prefetchable)
Region 2: Memory at ffe7fc00 (32-bit, prefetchable)
Region 3: Memory at ffe7fc00 (32-bit, prefetchable)
Region 4: Memory at ffe7fc00 (32-bit, prefetchable)
Region 5: Memory at ffe7fc00 (32-bit, prefetchable)
00: 86 80 08 00 43 01 80 00 00 00 00 ff 00 00 00 00
10: 08 fc e7 ff 08 fc e7 ff 08 fc e7 ff 08 fc e7 ff
20: 08 fc e7 ff 08 fc e7 ff 08 fc e7 ff 08 fc e7 ff
30: 08 fc e7 ff 08 fc e7 ff 08 fc e7 ff ff 00 00 00

01:00.0 Class 0600: 8086:1225 (rev 02)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
Status: 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 2 min, 6 set
00: 86 80 25 12 47 01 00 22 02 00 00 06 00 06 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00

01:0d.0 Class 0100: 9004:7078 (rev 03)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR+
Latency: 8 min, 8 max, 64 set, cache line size 08
Interrupt: pin A routed to IRQ 11
Region 0: I/O ports at fc00
Region 1: Memory at ffcff000 (32-bit, non-prefetchable)
00: 04 90 78 70 17 00 80 82 03 00 00 01 08 40 00 00
10: 01 fc 00 00 00 f0 cf ff 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 08 08

01:0e.0 Class 0100: 9004:7078 (rev 03)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR+
Latency: 8 min, 8 max, 64 set, cache line size 08
Interrupt: pin A routed to IRQ 10
Region 0: I/O ports at f800
Region 1: Memory at ffcfe000 (32-bit, non-prefetchable)
00: 04 90 78 70 17 00 80 82 03 00 00 01 08 40 00 00
10: 01 f8 00 00 00 e0 cf ff 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 cd ff 00 00 00 00 00 00 00 00 0a 01 08 08

+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+ Eric PAIRE
Email : e.paire@gr.opengroup.org | The Open Group - Grenoble Research Institute
Phone : +33 (0) 476 63 48 71 | 2, avenue de Vignate
Fax : +33 (0) 476 51 05 32 | F-38610 Gieres FRANCE

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