I noticed that in the latest development kernels there is support for
the MTRR registers, which allows you to enable write combining for
the linear framebuffer of a graphics card on PPro and PII systems. I
am curious about how this works. I took a quick look at the source
for this in the kernel, but the module was huge and went way over my
head (all the __SMP__ and other #defines make my head spin!).
Anyway, how does the kernel find out how to program the MTRR
registers for the framebuffer, or does is simply export services that
user land code can call the enable MTRR write combining for the LFB?
If it allows user land app (like our code!) to do this, what is the
system call for this and is there any documentation on it?
One of the reasons why I am curious is that it is vitally important
when you re-program the MTRR's for the hardware linear framebuffer of
the graphics device that you don't simply block enable it for the
entire amount of memory that the PCI device has mapped. The reason
for this is that many cards (ATI is one) map their MMIO registers at
the end of the framebuffer memory, and if you enable write combining
on the MMIO registers the acceleration code freaks out and does not
work properly. In order for this to work properly you can only enable
it up to the next 512Kb boundary before the MMIO registers (since the
MTRR's require a 512Kb aligned length to work properly).
Regards,
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