Re: Strange interrupt behaviour

Gabriel Paubert (paubert@iram.es)
Fri, 17 Jul 1998 14:16:27 +0200 (METDST)


On Sun, 12 Jul 1998, Gerard Roudier wrote:

> You are making too much assumptions on the actual effect of "mask off IRQ"
> and "ACK the interrupt" or you are only addressing the edge triggered
> interrupt scheme in when interrupts are handled by one processor.
>
> PCI has defined an "Interrupt acknowledge" transaction, but it seems that
> devices donnot implement it. So the only way to actually "ack the
> interrupt" is to remove the cause of this interrupt and only the device
> driver is able to do that.
>

[Back after 2 weeks on holiday :-) and 3000+ messages in the mailbox :-(]
It is not that devices do not implement the Interrupt acknowledge, it is
that the PCI specification states that interrupt acknowledge will be
handled by a single agent on bus 0. It is the PCI<->ISA bridge which does
this since it integrates the dual 8259. This cycle is performed even when
using the APIC when the mode is set to ExtInt (actually there is at least
one PCI<->ISA bridge on which you can disable the PCI Interrupt
Acknowledge response, the 82378ZB and its sibling Winbond 83C553F).

The catch is that the PCI interrupt acknowledge cycle was designed to be
compatible with the braindead PIC system, not as a broadcast cycle
during which interrupting devices fight for putting their vector
on the bus through some arbitration system. Hence the
horror story known as A(wkward)PIC...

> If you want to mask an IRQ when you are using an IOAPIC, then you have to
> mask it at IOAPIC level and this uses the APIC BUS and so this operation
> cannot be atomic but is totaly asynchronous.

Not exactly, the masking is made by accessing the IO-APIC registers
through a cascade of buses (see next paragraph). But there may be a
message from the IO-APIC to the processor in fly for the same interrupt
at the same time.

For performance reasons, you should refrain from accessing the IO-APIC too
often, it is located on the ISA bus through an 8-bit interface. Adding to
this the fact that it uses an indirect index/data register which means
that each register read or write requires 8 8-bit ISA cycles :-( Did
anybody measure how long it takes to access this beast ?

Gabriel.

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