On Sat, 11 Jul 1998, Steven N. Hirsch wrote:
> Your latest Cyrix patch seems to operate correctly on my P150+, but the
> /proc/cpuinfo file is a bit odd:
This one was nasty oversight, but I think I got it! :)
> processor : 0
> cpu family : 5
> model : xIns 2x Core/Busteadck
> ^^^^^^^^^^^^^^^^^^^^
^^^^ ^^^^^
These are the second and third part of the vendor id from the cpuid.
> cpuid level : 3145729
> ^^^^^^^^
Same here as above, cpuid_level is overitten by the vendor string. The
error is in bugs.h (check_cx686_cpuid_slop) I did:
cpuid(0, &boot_cpu_data.cpuid_level,
(int *) &boot_cpu_data.x86_vendor_id,
(int *) &boot_cpu_data.x86_vendor_id+8,
(int *) &boot_cpu_data.x86_vendor_id+4);
instead of,
cpuid(0, &boot_cpu_data.cpuid_level,
(int *) &boot_cpu_data.x86_vendor_id,
(int *) (&boot_cpu_data.x86_vendor_id+8),
(int *) (&boot_cpu_data.x86_vendor_id+4));
ANSI C precedence rules, Duh!!!
> Jul 11 09:08:37 cy kernel: Calibrating delay loop... 119.60 BogoMIPS
It also seems that you're getting the right BogoMIPS from the beginning.
I haven't checked 2.1.109 yet, does it include the calibrate_delay
alignment patch? If that the case, I'm guessing the alignment patch also
fixes the problems with the Cyrixes. It seems that we might not need to
reset the SLOP bit in the 686(L)'s after all.
> Jul 11 09:08:37 cy kernel: Memory: 63160k/65536k available (908k kernel code, 392k reserved, 1032k data, 44k init)
> Jul 11 09:08:37 cy kernel: Checking if this processor honours the WP bit even in supervisor mode... Ok.
> Jul 11 09:08:37 cy kernel: CPU: Cyrix 6x86 2x Core/Bus Clock stepping 2.5
After this line on bootup you should get a recalibration on the BogoMIPS,
could you please compare if the number is the same as the first time
through. Also, I would be good to get more datapoints on the BogoMIPS
issue. Anyone else with a Cx686 or 686L care to test?
> Thanks again for your efforts, and I'll be glad to test any fixes.
You're welcome! New patch attached ;-)
[*** Andre, please check this out for the 2.0.x patch! ***]
Cheers,
Rafael
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