> On Fri, 10 Jul 1998, Richard B. Johnson wrote:
>
> > We need to use timer-channel 0, connected to IRQ0 for context-switches
> > because it's the highest priority interrupt. However, we could use the
> > CMOS timer, which is connected to a lower-priority interrupt, for the
> > jiffy-counter and basic time functions. Or the PLL attempt, really
> > a frequency-lock, already implemented, could sync to the CMOS timer.
>
> Hey, what's the problem with reprogramming the 8259s so that IRQ8 were
> the highest priority interrupt?
>
> --
Well, for one, its connected to the first chip through IRQ2, the
'cascade', so to make it the highest priority, the first chip would
have to be even higher-priority which, by definition, is impossible.
Then, the SMP machines don't use these controllers at all unless the APIC
is broken.
Cheers,
Dick Johnson
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