Mike Jagdis wrote:
>
> On Sun, 24 May 1998, Phil's Kernel Account wrote:
>
> > #BTW I have been told that the new Cyrix MII CPUs have the "Coma bug"
> > #fixed. More info on this as soon as I can get a part for tests.
> >
> > Consider this confirmed. The mII *IS* a Cx6x86MX core, but with some MAJOR
> > changes. Among them includes the fixing of the Coma bug, as well as some
> > pretty big updates to VSPM, and the AEU. Can we PLEASE use VSPM actively
> > now? I *LIKE* the idea of addressing memory in 4G blocks. :)
>
> I was under the impression VSPM had been dropped from the MX. Or was
> it just removed from the documentation?
VSPM was dropped in the 6x86MX and the registers used by VSPM control on
the 6x86 were allocated to Translation Lookaside Buffer (TLB) testing in
the 6x86MX.
There are no signs of VSPM in the MII Data Sheet, and I think that Cyrix
has definitely abandoned the idea (you and I have already exchanged some
emails on the subject, and I had reported < 0.5% observed performance
improvements when using your very neat VSPM patch). Anyway, Microsoft is
never going to support a feature that is not available on Intel chips...
The MII architecture is essentially identical to the 6x86MX, but is
implemented in 0.25 micron technology. IBM is selling the same silicon
labeled as 6x86MX-PR300 and 6x86MX-PR333.
I think Cyrix has decided to (finally) drop the PR rating, but in doing
so also changed the name of the chip from 6x86MX to MII. Right now they
are not shipping these parts in volume. As soon as I get one for tests,
I'll make the relevant info available on the kernel mailing list
(stepping number, etc).
Regards,
------------------------
André Balsa
andrebalsa@altern.org
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