> Sorry, but I *am* right. Look carefully at the code. It is *impossible*
> for the Cyrix to generate a divide-by-zero Oops (which has been
> experimentally verified by numerous sources) *unless* the Cyrix is
> zero-ing the top 32 bits of the TSC on HLT. I call that "destroying the
> TSC".
>
> It is impossible to Oops if the Cyrix is just stopping the TSC.
> The times will be off, but no Oops.
Ok, guys lets get over this one. I'm attaching ver.2 of the Cyrix/C6 TSC
tester (sorry for all those lines), could people with these chips check it
out. Mine, 686MX step.3, doesn't clobber the TSC when SOH. Heck, it even
increments the top bits ;-)
> > We have two cases:
> >
> > 1) If the Suspend-on-Halt feature is disabled (default state after a
> > reset), the Cyrix 6x86MX will behave just like the Intel part.
>
> I'll believe you there. *BUT* this needs to be documented in big red
> letter somewhere: DON'T SUSPEND-ON-HALT. *However* it seems that many
> people really really like Suspend-on-halt because it keeps their
> processors cooler than the summer sidewalk in new york; it seems being
> safe and allowing people to use power-saving on their CPUs is not so
> unreasonable an option.
>
> I'll leave this choice up to the Cyrix community. At the moment Linus has
> implemented 'prevent-the-Oops,' which I think is a reasonable decision.
>
> > 2) If Suspend-on-Halt is _explicitly_ enabled (e.g. using a utility
> > called set6x86), the Cyrix 6x86MX acts like the Centaur C6 step 0, i.e.
> > it stops the TSC when Halted.
>
> See above. The Cyrix is trashing the TSC. There's no other way it can
> Oops.
We need to determine which Cyrix are those, so far I heard there are 686MX
rev.0,1,2,3,4 and 6. Rev.3 is fine, and I believe someone said the same
for rev.6. Anyone who can test the other revs? I've also been told that
the C6 also tests with the included program, I've not confirmed this.
[Now if we could just get SOH and a TSC based do_timeoffset together we
would also solve the problem with APM also, and get the extra performace,
right?]
-- Rafael------------------------------------------- /* Cyrix 686MX (and Centaur C6) TSC tester V2, must compile with optimizations due to inline asm in io.h */ #include <stdio.h> #include <unistd.h> #if (__GNUC__ == 2) #include <sys/perm.h> #endif #include <asm/io.h>
/* asm macro to read the tsc */ #define rdtsc(LSW, MSW) asm("rdtsc" : "=a" (LSW), "=d" (MSW) )
void do_test(int times) { unsigned long msw, lsw, prev;
rdtsc(prev, msw); for (; times; times--) { sleep(1); rdtsc(lsw, msw); /* unsigned sub handles underflows correctly up to 4GHz CPU :-) */ printf("MSB: %lx,\t%10lu cycles/sec.\n", msw, lsw - prev); prev = lsw; } }
/* NOTICE: assumes the SOH is disabled at entry; leaves it disabled */ int main() { char data;
if (ioperm(0x22, 2, 1) != 0) exit(1);
/* test w/ suspend on halt enabled */ outb(0xc2, 0x22); data = inb(0x23); outb(0xc2, 0x22); outb(data | 8, 0x23); do_test(5);
/* test w/ suspend on halt disabled */ outb(0xc2, 0x22); data = inb(0x23); outb(0xc2, 0x22); outb(data & ~8, 0x23); do_test(5);
return 0; }
------------- sample output --------------- MSB: 191, 282912 cycles/sec. MSB: 191, 520528 cycles/sec. MSB: 191, 469222 cycles/sec. MSB: 191, 442800 cycles/sec. MSB: 191, 531261 cycles/sec. MSB: 191, 151240577 cycles/sec. MSB: 191, 151502263 cycles/sec. MSB: 192, 151502066 cycles/sec. MSB: 192, 151502532 cycles/sec. MSB: 192, 151501994 cycles/sec.
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