Re: How to compile a Pentium II

Rogier Wolff (R.E.Wolff@BitWizard.nl)
Fri, 15 May 1998 08:25:21 +0200 (MET DST)

H. Peter Anvin wrote:
>
> Followup to: <355B4CF7.4E43EAA6@pobox.com>
> By author: Brion Vibber <brion@pobox.com>
> In newsgroup: linux.dev.kernel
> >
> > >
> > > PII doesn't have MMX? Strange.
> >
> > PII does have MMX. (At least the sticker on my computer says so! ;) In
> > fact it's basically a PPro with MMX in a pretty little box with a slot
> > instead of a bunch of pins. I think the intended meaning was that the K6
> > lacks the PII's socket design, big cache, and MMX, but is similar in
> > internals (?).
> >
>
> Actually, the PII has an external L2 cache running at 2:1 clock
> vs. the core; the PPro has an internal L2 cache at 1:1 (faster).

I remember the PPro having L1 cache that was something like 15ns
access time (3 clocks), while the L2 cache was more like 35 ns (7
clocks).

Even if I'm wrong and the L1 cache is 5ns, and the L2 15ns, what
does a "clock speed" mean?

It depends on the application if you'd rather have 7 clocks at 200MHz
(35ns) or 3 clocks at 100 (30ns). (Assuming pipelined/burst).

Roger.

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