> > There may be a significant difference. For good performance pages should
> > be allocated with their physical addresses choosen such that maximum
> > cache hit rates can be achived. That's something which the current
> > buddy system for the free pages doesn't support. For RISC/os and IRIX
> > the performance difference accounts for 5 - 10%.
>
> Is this for the 2nd level cache? I thought the primary cache on MIPS
> were indexed by virtual addresses.
R2000/R3000/R6000 primary caches are physical indexed, R4xx0, R5xxx, R10000
primary caches are virtually indexed, physically tagged. Where available
secondary and L3 caches are physically indexed. R8000 primary I-caches are
virtually indexed and tagged with the virtual (!) address and ASID; R8000
data caches are virtually indexed and tagged with physically address and
ASID. R6000 / R6000A don't have a ``real´´ TLB but the TLB implemented as
part of the external primary cache which is physically indexed.
(What, your head is already exploding?)
For increased fun lots of CPU variations have been produced for specific
implementations with specific cache systems. There are over 70 available on
the market and more under development or only available in specific products,
so shame on me, I've lost track about all the technical details like
associativity. Oh, the TLB is actually also a kind of a cache and of course
there are certain variations available ...
The numbers have been benchmarked on R4000SC systems. The exact
implementation of this colouring stuff all these number obviously depends
from the exact type of cache system in use.
Cite Linus Torvalds ``Remind me never to program anything for MIPS´´ :-)
Ralf
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