> The border I'm talking about is the user<->kernel border. We don't do
> _anything_ to the TLB when crossing that border. At least not on
> decent RISC chips with block translation capabilities (maybe you have
> to do some weird things to accomodatestupid caches like the
> MIPS).
Accesses to KSEG0 where the kernel resides the CPU does not cause any TLB
faults. Similarly the fact that the caches of most modern MIPS CPUs are
virtually indexed is not overly relevant. Virtual indexed caches shurely
have been a good reason for serious swearing under OS implementors but also
helps to simply the CPU's pipeline structure significantly which again
help to improve the execution times. It's all about tradeoffs ...
Ralf
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