Re: SMP speed on 6x86 UP
Alan Cox (alan@lxorguk.ukuu.org.uk)
Fri, 20 Mar 1998 17:48:12 +0000 (GMT)
> The CR4 register on 6x86 is undocumented (and even illegal).
> On 6x86MX we got four bits in it:
> 2 = TSD(Time Stamp Disable), 3 = DE(Debugging Extensions),
> 7 = PGE(Page Global Enable), 8 = PCE(Performance Counter Enable)
>
> Can we move these insns downwards, until the processor vendor is detected?
> Or we delete %cr4 again after detecting a cyrix?
One problem - the code you are looking at should only be getting executed
on the real mode boot entry of the second or later _intel_ processor,
so Im baffled how it could be involved
Do nops to the same size as the jmp you added do anything.
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