> I tested the implementation of spinlocks in 2.1.89 and booted an SMP kernel
> on my single CPU machine (FIC PA-2010, VIA Apollo VP, 1xIBM 6x86-P166+ at
> 133 MHz) and the bogomips (= frequency in MHz on this CPU) dropped from 133
> to 33. Not only the bogusmips value drops but also the system performance.
> With CPU intensive code, I see exactly the same thing: 1/4 of the
> performance, I have with a UP kernel.
>
> Anybody got any idea. May the APIC code touch chipset or processor ports?
That rings a bell. The 6x86 configuration registers are accessed
via I/O ports 0x22, 0x23 which are, I think, where you expect to
find the APIC on an SMP system. Now I can see why you might want
to set up the APIC on an SMP board even with a single processor,
but you should *never* be writing to an APIC if the CPU is non-Intel.
If you do and the CPU is actually a 6x86 I would guess that the
most probable effect would be to disable the L1 cache - although
there a lot of other "interesting" things that could happen...
Mike
-- .----------------------------------------------------------------------. | Mike Jagdis | Internet: mailto:mike@roan.co.uk | | Roan Technology Ltd. | | | 54A Peach Street, Wokingham | Telephone: +44 118 989 0403 | | RG40 1XG, ENGLAND | Fax: +44 118 989 1195 | `----------------------------------------------------------------------'
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