r> Some architectures can use multiple page sizes in the TLB at the same time.
r> This would for example allow to map memory allocations > PAGE_SIZE using just
r> a single TLB entry if the circumstances are just right, thereby
r> reducing / eleminating TLB trashing. This should improve the performance
r> for huge apps quite a bit. Some architectures could partially get rid of
r> the sick effects of their virtual indexed primary caches as well. All that
r> is needed for this to work is to have sufficiently large physical pages with
r> sufficient alignment at hand.
r> Has anybody ever looked into implementing that? What architectures besides
r> MIPS could take advantage of such a feature?
The MPC860. We now have 8 MByte Page Table entries for the Kernel Address
Space and the Dual Ported RAM used to communicate with the CPM.
r> Ralf
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