Re: IRQ 255?

Pawel S. Veselov (vps@unicorn.niimm.spb.su)
Thu, 29 Jan 1998 21:54:34 +0300 (MSK)

Hello, Rik!

On Thu, 29 Jan 1998, Rik van Riel wrote:

[ skipped ]

>HSYNC/VSYNC notification... Sounds like it's time for the
>cheap-light-pen trick :-)

I don't sure for 100%. There is some information about interrupts and
[V/H]sync'ing, but I can't figure out, what they call under interrupt...

---
Input Status 0 Register		(STATUS_0)
Read Only			Address : 3C2H


Bit 7	CRT INTPE - CRT Interrupt Status
	0 - Vertical retrace interrupt cleared
	1 - Vertical retrace interrupt pending



---
Vertical Retrace End Register (VRE) (CR11)
Read/Write			Address:3?5H, Index 11H


Bit 4	CLR VINT - Clear Vertical Retrace Interrupt
	0 - Vertical retrace interrupt cleared
	1 - The flip-flop is able to catch the next interrupt request


	At the end of active vertical display time, a flip-flop is set
	for a vertical interrupt. The output of this flip-flop goes to the
	system interrupt controller. The CPU has to reset this flip-flop by
	writing logical 0 to this bit while in the interrupt process, then
	set the bit to 1 to allow the flip-flop to catch the next interrupt
	request. Do not change the other bits of this register. This bit is
	cleared to 0 by the BIOS during a mode set, a reset or power-on.


Bit 5	DIS VINT - Disable Vertical Interrupt
	0 - Vertical retrace interrupt enabled if CR32_4 = 1
	1 - Vertical retrace interrupt disabled. This bit is cleared to 0
	    by BIOS during a mode set, a reset or power-on



---


To enable interrupt one should be able to write with MMIO. If somebody is
interested in, I will publish this information.


Bye.

--
I hold it, that a little rebellion, now and then, is a good thing...
		-- Thomas Jefferson



--
    With best of best regards, Pawel S. Veselov (aka Black Angel)
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