> > Sorry, 'fraid I've got you there. I made it very clear when I purchased
> > this that it be Post Step2, Rev5. CPU itself has the revision markings for
> > Step2, Rev7. DOS utilities report same. However, I think this is an issue
> > with Cyrix, where they aren't specifying very well between revisions
> > somehow. (FYI; Step2, Rev5 and earlier have some major problems with VSPM.
> > Pre-Step1,Rev7 will NOT support VSPM.)
I didn't know step 2 was up to rev 7 anyway...
> Not to cause too much noise, but VSPM seems to work fine on my Step 1 Rev.
> 5. Haven't had any problems for a long time (since the first 2.0.x cyrix
> patch)
With step 1 rev 5 the CPU crashes if certain combinations of
flags are set in a VSPM entry, has problems at the boundaries
between VSPM entries and only seems to have four VSPM slots
even though the table index is 3 bits. Rev 6 fixes the flags
problem and, I think, changes the boundary problem but doesn't
fix it. Rev 7 fixes the boundary problem as well but still
only has four slots instead of eight. Higher than rev 7 and
step 2 chips are believed to behave at least as well as 1 rev 7.
My VSPM Cyrix patch is aware of the differences and silently
works round them. This should not be surprising since, as far
as I am aware, the only place it is all documented is in the
Linux patch. Clearly someone at Cyrix has been working on VSPM
at various times but no one I could reach even knew what is was.
Mike
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