Hmmm. Actually some of us work for CAD companies (I've seen Linux
users from Synopsys, Cadence and friends) I personally don't consider
layout and verification such a big problem. I don't think that
company management would mind if quality control group would use some
huge cores from GNU project to test place'n'route and verification
tools. I believe they would even like it -- no NDA's to sign :-). Side
effect - we get layout for free :-). The only problem - we need enough
people who know Verilog (VHDL) and are willing to contribute some
of their free time to this project.
Eugene
-- Eugene Anikin http://home.sprynet.com/sprynet/anikin anikin@cdac.com anikin@sprynet.com ____________________________________________________________________ Cascade Design Automation - one easy step from Language to Layout