The point is that the rs6000/ppc hardware cannot support a full virtual
memory map with the hash tables. As such they are not page tables: they
are only _partial_ page tables.
A page table allows for looking up a virtual address.
- The IBM hash tables do not. If I create a virtual mapping that happens
to have more than eight (or is it sixteen?) aliases for the hash, the
hash table can no longer hold them all. Ergo the kernel cannot consider
the hash tables to be a page table.
A TLB allows for fast lookups of the parts of the VM space that the CPU is
aware of at the moment.
- Which is exactly what the IBM hash tables do.
"Hash table" just happens to be the IBM implementation for the TLB. Others
have done similar things to expand the TLB outside the chip (some sparc
chips - the more braindamaged ones, to be exact). Making it external to
the CPU doesn't make it a page table, it only makes it slower (but in all
fairness it also makes it bigger, which is obviously why they do it).
Linus