Re: TritonII IDE interface not PCI compliant?

Rogier Wolff (R.E.Wolff@BitWizard.nl)
Tue, 17 Jun 1997 10:38:43 +0200 (MET DST)


I wrote:
>
>
> Hi,
>
> Has anybody here seen anything like the following?
>
> If my preliminary tests are correct, the IDE interface from the
> Triton/Natoma chipset, the 82371SB chip, is not using the "Latency"
> counter.

I've now concluded that by doing something like a memcpy, the CPU
can starve PCI busmasters to death.

Any PCI busmaster with a real-time requirement will suffer from this
problem. Not included are "IDE" busmasters. They simply tell the
IDE drive to hold on to the data a little longer. With Asynchronous
targets, SCSI can do the same. I don't know enough about SCSI to say
something about sync mode.

Most ethernet controllers ARE affected: these usually have less than
a packet worth of buffer, and will need to dump some into main memory
before the buffer overruns. The Intel 82557 (eepro100) has a 3k buffer,
probably because Intel knows of this problem.

The Linux kernel cannot do much about this. This is a hardware issue.
You now do know that you have to check any "overrun" bits before
trusting the data that a PCI busmaster chip put into memory....

I've always thought that in a PCI system, the CPU had the lowest
priority. This would grant the PCI busmasters the bus for the time
they need, and leave all the rest to the CPU.

Anyway, I might still contact Intel about this (Intel CPU, Intel
chipset), and see what they have to say about it.....

Roger.