>
> Hi,
>
> Has anybody here seen anything like the following?
>
> If my preliminary tests are correct, the IDE interface from the
> Triton/Natoma chipset, the 82371SB chip, is not using the "Latency"
> counter.
>
> I have a board in my computer that requires about 6Mb per second
> throughput on the PCI bus. That's not nearly enough to saturate
> the bus right? Anyway, that board has a buffer for 128 bytes.
> That is enough for 20 microseconds of data, but it will only request
> the bus when the buffer is about half full. Thus, it needs the bus
> within a span of 10 microseconds. If my calculations are correct,
> a latency of 32 cycles means about one microsecond.
>
> With two or three devices active on the bus I'd expect a max latency
> around a few microseconds. However my board reports that it gets
> locked out for long enough (10 us) that it gets a buffer overrun.
>
> This is my IDE interface according to /proc/pci:
>
> Bus 0, device 1, function 1:
> IDE interface: Intel 82371SB Natoma/Triton II PIIX3 (rev 0).
> Medium devsel. Fast back-to-back capable. Master Capable.
> Latency=32. I/O at 0xe800.
>
> Whenever I do disk access (dd if=/dev/hda of=/dev/null works nicely),
> I get tons of overruns from the other board.
>
> To me this indicates that the 82371SB isn't honoring the latency
> counter. Anybody have a different explanation? Anybody see the same?
>
I assume that you are able to read your board quickly enough so you
can empty its buffer fast enough to prevent a buffer overrun if your
disk drive isn't running.
A quick and dirty fix is to clear the interrupts during this read so the
IDE driver doesn't take the CPU away from you when you need it most.
The real fix is probably DMA (hense SCSI).
I don't think the IDE interface is capable of DMA. This means that the
driver will write the "sector-buffer" using the CPU, out a port. This
will prevent the bus from being shared at the time. What you need is
a SCSI board that does DMA "bus mastering", much different than so-called
IDE "master capable". This causes bus activity to be in bursts, allowing
other devices to use the bus also. The DMA bursts run a "RAM speed" with
spaces in-between. The average transfer rate is slower than "RAM speed", but
there is plenty of time for other devices (including RAM) to share the
bus.
Cheers,
DJ
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Richard B. Johnson
Analogic Corporation
Email : rjohnson@analogic.com, johnson@analogic.com
Penguin : Linux version 2.1.42 on an i586 machine (66.15 BogoMips).
Warning : It's hard to stay on the trailing edge of technology.
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