Re: 2.0.x Cyrix patch on 2.0.30
Derek Fawcus (df@eyrie.demon.co.uk)
Tue, 22 Apr 1997 21:36:57 +0100 (BST)
Mike Jagdis wrote:
> On Fri, 18 Apr 1997, Derek Fawcus wrote:
> > Something else that looks useful is the ability (only on the K5?) to
> > not flush certain TLB entries on CR3 reloads. I believe that the Cyrix
> > 6x86 also has a similar facility which actually locks some TLB enties
> > in a special seperate table.
>
> I can't remember seeing anything about locking TLBs. Maybe they were
> talking about VSPM mappings (which have some, ah, "interesting"
> problems anyway :-) ).
Yeah - I misremembered, I'd been reading too many data sheets and got
their features confused. It was the VSPM mapping's I was thinking about.
It was their method of set up I was thinking about.
I also seem to remember (thought I could be confused again) that the
ARM 810 processor allows TLB and/or Cache lines to be locked down. I
guess I'll have to see if I can find the .pdf files again.
DF
--
Derek Fawcus df@eyrie.demon.co.uk