Re: 2.0.x Cyrix patch on 2.0.30
Mike Meissner (meissner@cygnus.com)
Mon, 21 Apr 1997 16:42:10 -0400
Alan Cox writes:
| > of locking down an L1 cache line. Anyone care to speculate how that
| > could benefit us? Cyrix suggest that since L1 accesses are as fast
| > as register accesses you could use it to implement large register
| > files. We've all complained about how few general purpose registers
| > x86 chips have...
|
| Having L1 cache at register speed really requires someone totally rewrites
| the x86 machine description for the Cyrix to do cache line allocation for
| automatic variables and cache line scheduling on variables.
Umm, the storage allocation part is in machine independent code in GCC
(in function.c), not in x86 specific backend pieces (that's not to say
that there would be no machine dependent changes). It would be a nice
project (though because it is MI code, you have to make sure you don't
break all of the other machine descriptions).
| Big job but might be quite a win
Assuming somebody does it.
--
Michael Meissner, Cygnus Solutions (East Coast)
4th floor, 955 Massachusetts Avenue, Cambridge, MA 02139, USA
meissner@cygnus.com, 617-354-5416 (office), 617-354-7161 (fax)