Re: 2.0.x Cyrix patch on 2.0.30

Derek Fawcus (df@eyrie.demon.co.uk)
Fri, 18 Apr 1997 01:02:18 +0100 (BST)

Cameron MacKinnon wrote:
> If you want to be REALLY, WICKEDLY COOL, you could patch in support for
> the K6's new syscall instruction: Fast ring 0/3 switching. Extra points
> if you can make it work without having to recompile libc. Then you can
> time thing and tell me how much faster than Intel it is, as I can't find
> cycle counts anywhere. 8-)

I've just read the BIOS design note on that (not yet tackled that data
sheet), and it requires a fixed layout in the GDT (not a problem), and
flat 4G segments CS and SS. I think that this'll require a change as
doesn't the x86 kernel still rely upon the user segments being 3G(ish).
If so we'd have to use the paging h/w to protect all of the kernel.

Also it doesn't save the processor state other than EIP - and trashes
ECX too boot. Once you've added in the code to save and restore the
registers it obviously gets a bit slower. However the exercise may
still be worth it - anyone want to count instruction cycles?

Something else that looks useful is the ability (only on the K5?) to
not flush certain TLB entries on CR3 reloads. I believe that the Cyrix
6x86 also has a similar facility which actually locks some TLB enties
in a special seperate table.

DF

-- 
Derek Fawcus                                        df@eyrie.demon.co.uk