RE: PCI bus and shared interrupts, proposal.

Chel van Gennip (linux@vangennip.nl)
Sun, 6 Apr 1997 9:59:12 +0100 (WETDST)

Chel van Gennip wrote:
> I have posted this message on comp.os.linux.development.system, but I think
> maybe this is a better place for discussion.
> The interrupt allocation scheme of new AMI bioses introduces some
> problems.
>
> After detecting some problems I found out there is a problem
> with IRQ assignment on the PCI bus and the Linux
> implementation of interrupt handling.
>
> My problem:
> The Intel Venus PPRO board (VS440FX) assigns the same IRQ to
> both a network card and a SCSI card.
> The SCSI drivers registers the IRQ with the SA_INTERRUPT flag,
> the network driver without this flag, so the IRQ can not be
> shared.
>
> Discussion with my Intel distributer points out the following
> PCI standard requirements:
>
> - The PCIBIOS should assign interrupts for the different
> devices.
> - The PCI INTA and INTB line should not be assigned the
> same IRQ
> - The same IRQ can be assigned to different devices. This
> should be handled by the driver.
> - Assigned IRQ's can be read by the PCIBIOS call
> pcibios_read_config_byte()
> - Assigned IRQ' can be changed by the PCIBIOS call
> pcibios_write_config_byte()
>
> I should verify if this is correct, if so these rules are
> stupid. At least the second rule is without any meaning if
> both the assigned interrupt lines can be randomly shared with
> interrupt lines of other cards, eg. cards of the same type and
> make.
>
> If the rules are correct, I think we need handling of this in
> the Linux kernel, otherwise a lot of problems will rise.
>
> To deal with this I think IRQ should be assigned by the kernel
> and not by the PCIBIOS.
>
> The minimum requirement is to have separate IRQ's for the
> interrupts with the normal interrupt handler and for the fast
> interrupt handler (SA_INTERRUPT flag), of to find a way to
> share normal and fast interrupts.

I have done some searching on the net and found some interesting
information.

If my interpretation of this information is correct, then it is
legal to have eg. INTA of slot 1 connected in hardware to INTB of
slot 2. As a result of this the second SCSI device of an Adaptec
3940 will by definition share the IRQ with one of the devices
in the other slots.

If this is true the proposed solution won't work. The ONLY possible
solution will be to make ALL interrupts shareble!

I am not so familiar with these hardware aspects, so please comment.

Result of the net search:

http://www.delorie.com/djgpp/doc/rbinter/ix/1A/B1.html
http://www.delorie.com/djgpp/doc/rbinter/
http://www.cs.cmu.edu/afs/cs.cmu.edu/user/ralf/pub/WWW/files.html

1AB10F

Category: expansion bus BIOSes

INT 1A - Intel PCI BIOS v2.1+ - SET PCI IRQ

AX = B10Fh
BH = bus number
BL = device/function number (bits 7-3 device, bits 2-0 function)
CH = number of IRQ to connect
CL = number of interrupt pin (0Ah=INTA# to 0Dh=INTD#) to reprogram
DS = segment/selector for PCI BIOS data
(real mode: F000h; 16-bit PM: physical 000F0000h; 32-bit PM:as
specified by BIOS32 services directory)
Return: CF clear if successful
AH = 00h
CF set on error
AH = error code (59h) (see #0650)
Note: assumes that the calling application has determined the IRQ routing
topology (see AX=B10Eh), has ensured that the selected IRQ will not
cause a conflict, and will update the interrupt line configuration
register on all devices which currently use the IRQ line
SeeAlso: AX=B10Eh

1AB10EBX0000

Category: expansion bus BIOSes

INT 1A - Intel PCI BIOS v2.1+ - GET IRQ ROUTING INFORMATION

AX = B10Eh
BX = 0000h
DS = segment/selector for PCI BIOS data
(real mode: F000h; 16-bit PM: physical 000F0000h; 32-bit PM: as
specified by BIOS32 services directory)
ES:(E)DI -> IRQ routing table header (see #0666 at AX=B406h)
Return: CF clear if successful
AH = 00h
BX = bit map of IRQ channels permanently dedicated to PCI
WORD ES:[DI] = size of returned data
CF set on error
AH = error code (59h) (see #0650)
WORD ES:[DI] = required size of buffer
SeeAlso: AX=B10Fh,AX=B406h,INT 2F/AX=1684h/BX=304Ch

Table 666

Format of Intel Plug-and-Play AUTO-CONFIGURATION PCI IRQ routing header:
Offset Size Description
00h WORD length of IRQ routing table buffer
02h DWORD -> IRQ routing table array buffer (see #0667)

Table 667

Format of Intel Plug-and-Play ACFG PCI IRQ routing table entry [array]:
Offset Size Description
00h BYTE PCI bus number
01h BYTE PCI device number (bits 7-3)
02h BYTE link value for INTA#
(if non-zero, wire-ORed together with any other PCI interrupts
with same link value)
03h WORD IRQ connectivity bit map for INTA#
(standard AT IRQs to which PCI interrupt can be routed)
05h BYTE link value for INTB#
06h WORD IRQ connectivity bit map for INTB#
08h BYTE link value for INTC#
09h WORD IRQ connectivity bit map for INTC#
0Bh BYTE link value for INTD#
0Ch WORD IRQ connectivity bit map for INTD#
0Eh BYTE (PCI BIOS v2.1+) device slot number (00h = motherboard)
0Fh BYTE reserved
Note: each item in the routing table corresponds to a motherboard PCI
device or PCI slot
SeeAlso: #0666
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