just wondering if ring 3 code could use 4MB pages.
When i have the following page dir entry:
_PAGE_TABLE | _PAGE_4M | 4mb_aligned_phys_addr
Kernel space sees phys_addr correctly, but user space doesnt. Does this
mean that 4MB pages are only for ring0 code? Has anyone experimented with
this one?
Have you played around with different protection bits to see if that
changes the situation?
ps. and i got faults when phys_addr wasnt 4mb aligned ... does it really
have to be 4mb aligned?
If Intel implemented this the straightforward way, yes they must be
4mb aligned physically. Essentially they probably (and this is
exactly how it works on the SRMMU Sparc mmu's) do this:
4MB PTE (imaginary)
----------------------------------------
| Physical Page | PROT |
----------------------------------------
31 8 7 0
Virtual Address
----------------------------------------
| Virtual Page | Virtual Offset |
----------------------------------------
31 22 21 0
The MMU translates these two things into a physical address as:
PhysAddr = (PhysPage[31:22] | VirtOffset[21:0]);
So the physical address in the 4MB pte would in fact need to be 4MB
aligned and the lower PhysPage bits just get ignored during address
translation.
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David S. Miller, davem@caip.rutgers.edu /_____________/ / // /_/ ><