Re: [PATCH v5] ASoC: wm8978: add missing BCLK divider setup

[Sune Brian]

Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx> 於 2025年10月9日 週四 上午1:16寫道：

> [1] https://www.nxp.com/docs/en/user-manual/UM11732.pdf

I am curious. With this codec WM8978.
Can you set a LRCLK rate that is not relied on MCLK+BCLK ratio from
first place when codec is in master mode.
Can you request a sample rate that requires the concept of extra bit
clock arbitrary higher in one extra order?
Very curious on such idea.

If possible maybe some examples can help.