Re: [PATCH v3] ASoC: wm8978: add missing BCLK divider setup

[Mark Brown]

On Tue, Oct 07, 2025 at 11:55:29PM +0800, Sune Brian wrote:
> Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx> 於 2025年10月7日 週二 下午11:21寫道：

> > Apologies but just realised there is still one small problem here.
> > You want to match the closest BCLK that is over your target rate,
> > if the BCLK is too slow the system won't work. As your bclk_divs
> > array is sorted I think you can do something like:

> Not too understand what is the issue.
> The idea is setting the initial value to max any diff that is smaller
> will update bclkdiv index,
> If the maximum LUT 32 still not met then it is what it is.
> mclk / 32 is the bclk, unless you want an error message.

Consider the case where the BCLK needed is 100 and SYSCLK is 198.
Dividing by 1 will result in an absolute difference of 98 and a BCLK of
198 while dividing by 2 will result in an absolute difference 1 and a
BCLK of 99 which is lower than the required BCLK.

Attachment: signature.asc
Description: PGP signature